1. Field of the Invention
This invention generally relates to semiconductors and methods for writing data into the semiconductor device, and more particularly, to a semiconductor device having multiple reference levels and a method for writing the data into the aforementioned semiconductor device.
2. Description of the Related Art
The semiconductor memories are categorized into volatile ones that lose the information therein and non-volatile ones that retain the information therein, when the power turns off. Flash memories, in which the rewriting time is shortened by erasing the data at one time, are well known as a representative of the non-volatile ones.
This type of flash memory includes reference cells such as a reference cell for read, another reference cell for program, another reference cell for erase, another reference cell for convergence, and the like. Generally, each device has only one reference cell level in each of the reference cells.
FIGS. 1A and 1B are views illustrating data determination of the memory cell. In FIG. 1A, a Vg-Id characteristic curve 40 shows the characteristics of the reference cell transistor. A Vg-Id characteristic curve 41 shows the characteristic of the memory cell transistor that is erased, that is, the characteristic of the memory cell transistor that stores data of 1. A Vg-Id characteristic curve 42 shows the characteristic of the memory cell transistor that is programmed, that is, the characteristic of the memory cell transistor that stores data of 0. As shown in FIG. 1A, the same voltage is applied to the gates of the memory cell and the reference cell on the flash memory. For example, at the time of reading, if the current value that flows through the memory cell is higher than that flows through the reference cell, the data is determined as “1”. If the current value that flows through the memory cell is smaller than that flows through the reference cell, the data is determined as “0”. As will be seen in FIG. 1A, current Iread is greater than current Izero and less than current Ione.
However, the flash memory stores or does not store an electron in the floating gate to control a threshold value Vth of the memory cell transistor, and it is determined the current volume that is passed by applying arbitrary gate voltage. In this type of flash memory, the threshold value Vth of the memory cell that stores an electron may be lowered over time after releasing the electron, as the rewriting time into the memory increases, for example. In contrast, the reference cell in which the rewriting operation is not performed has a constant reference level, which is the threshold value.
As shown in FIG. 1B, the Vg-Id characteristic curve 42 is shifted to the left to be something like a Vg-Id characteristic curve 43, and a current Izero that is to be flown through the memory cell flows more than a current Iread, although the current Izero is originally smaller than the current Iread. This causes a problem in that the data of the memory cell is considered as the data “1”, although the data has to be determined as “0”, leading to a defect in some cases. It is necessary to determine whether the device is good or bad at a reference level Vth higher than the reference level for read in order to sense and recover the defect before the memory cell is detected as defective at the time of parity check or the like and the device operation is stopped.
However, in the aforementioned case, a different reference level circuit has to be provided in addition to the reference level that is normally used, causing a problem in that the area is increased. There arises another problem in that a trimming time is increased for adjusting the levels by providing multiple reference circuits.